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Comprehensive Modeling and Analysis of Front- and Back-Gated 6 nm HEMTs Utilizing High-K Dielectric Layers
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Keywords
High-electron-mobility transistor (HEMT)
Dual-gate architecture
High-K dielectric
Nanoscale devices
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Abstract
The performance and reliability of high-electron-mobility transistors (HEMTs) are critically influenced by gate architecture, dielectric passivation, and nanoscale scaling. This study presents a comprehensive modeling and analysis of front- and back-gated 6 nm HEMTs integrated with high-K dielectric layers, emphasizing electrostatic control, subthreshold behavior, and breakdown characteristics. Using a comparative framework of dual-gate configurations, device physics is modeled to assess threshold voltage modulation, short-channel effects, and leakage current suppression. Simulations demonstrate that high-K dielectrics enhance gate capacitance and mitigate short-channel degradation, resulting in improved subthreshold slope and drain current linearity. Critical evaluation of device trade-offs highlights the interplay between electrostatic integrity and parasitic capacitances, providing insights for nanoscale device optimization. The findings contribute to design strategies for high-performance, low-power HEMTs in advanced nanoelectronics applications.
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