A Novel Low-Power Multi-Threshold CMOS Level Shifter Architecture for Leakage Reduction

Abstract

Level shifters are integral components in modern multi-voltage CMOS systems, enabling reliable communication across voltage domains while maintaining signal integrity. However, conventional designs often suffer from significant static leakage, especially in sub-threshold or near-threshold operations, which severely impacts the energy efficiency of low-power digital circuits. This research presents a novel low-power multi-threshold CMOS level shifter architecture specifically designed for leakage reduction. The proposed design strategically integrates high-threshold (Vth) transistors to minimize subthreshold leakage during idle states and low-threshold transistors to preserve high-speed signal propagation in active modes. In addition, dynamic gate-level biasing is employed to adjust transistor thresholds based on operational conditions, further optimizing leakage and performance trade-offs.
Detailed simulation analysis demonstrates that the architecture achieves 38–42% reduction in static power relative to conventional single-threshold designs, while maintaining minimal propagation delay penalties (~5–7%) and reducing energy per transition by approximately 30%. The approach is benchmarked against prominent existing designs, including ultra-low voltage and sub-threshold level shifters, and consistently demonstrates superior leakage suppression, energy efficiency, and scalable implementation for deep-submicron CMOS processes. The findings provide critical insights into the practical application of multi-threshold techniques for low-power VLSI circuits, highlighting both theoretical underpinnings and system-level advantages. This work establishes a foundation for future research in energy-efficient inter-domain signaling, adaptive threshold management, and optimized design methodologies for next-generation ultra-low-power digital systems.