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Analysis of Thermal Behavior in FinFET Devices Considering Channel Fin Width and Operating Voltage
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Keywords
FinFET
Thermal Analysis
Channel Fin Width
Operating Voltage
Silicon Nanowire Transistor
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Abstract
The continuous scaling of CMOS technology into the sub-10nm regime has intensified the challenges associated with thermal management in nanoscale devices. Among emerging transistor architectures, FinFETs have demonstrated superior electrostatic control, reduced leakage, and improved performance compared to traditional planar MOSFETs. However, the three-dimensional structure of FinFETs introduces significant self-heating effects, which are strongly influenced by channel geometry and operating voltage. This study presents a comprehensive analysis of thermal behavior in FinFET devices, with particular emphasis on the interdependent effects of channel fin width and applied voltage on temperature rise, electrical performance, and reliability. Using a combination of analytical modeling and three-dimensional simulations, temperature profiles across different fin widths (5–10 nm) and voltage ranges (0.7–1.1 V) were systematically evaluated. The findings reveal that narrower fin widths exacerbate localized heating, while higher operating voltages amplify self-heating effects, resulting in increased threshold voltage shifts and reduced carrier mobility. Furthermore, the study highlights the critical role of oxide thickness and channel length in mitigating temperature-induced performance degradation, corroborating experimental observations reported in silicon nanowire transistors (AlAriqi et al., 2019). Comparative analysis with prior studies indicates that optimizing fin geometry and voltage bias can enhance thermal stability without compromising electrical performance, providing actionable design strategies for hardware engineers, embedded systems designers, and FPGA developers. This research contributes a predictive framework for thermal-aware FinFET design, offering insights into the trade-offs between performance, power, and reliability in ultra-scaled devices. The outcomes of this study are expected to inform both device-level design decisions and system-level integration strategies, ultimately supporting the development of high-performance, low-power nanoscale circuits.
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