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Design and Optimization of Low-Power VLSI Architectures for Mode Decision in Integer Motion Estimation of HEVC
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Keywords
HEVC
VLSI Architecture
Integer Motion Estimation
Low-Power Design
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Abstract
High Efficiency Video Coding (HEVC) represents a significant advancement in video compression standards, achieving superior coding efficiency at the cost of increased computational complexity. The mode decision process in integer motion estimation (IME) is a critical contributor to this complexity, directly impacting processing latency and power consumption. This research focuses on the design and optimization of low-power VLSI architectures tailored for mode decision in IME within HEVC encoders. Leveraging architectural parallelism, efficient data reuse, and selective computational pruning, the proposed designs demonstrate substantial power savings while maintaining high throughput. Comparative analysis with prior architectures highlights reductions in dynamic power, memory access overhead, and critical path delays. Experimental findings confirm the practical applicability of these architectures in embedded systems and FPGA implementations, providing a balance between energy efficiency and real-time performance.
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